Field of the Invention
The fabrication process of large-scale integrated electronic circuits begins with the layout design, which is intended to determine the functionality of the circuit. The layout defines the physical implementation of the circuit on a silicon wafer. Prior art methods for fabricating the circuit on the wafer are based on lithography, i.e., that, inter alia, the circuit layout is imaged first onto a mask and, then, onto the wafer through exposure of the mask.
Overall, a chip is fabricated in many steps. Each of the fabrication steps has an intrinsic inaccuracy that should ideally be taken into account as early as in the layout design. To that end, rules are provided (so-called design or layout rules) that must be taken into consideration in the layout design to ensure that the layout can actually be fabricated later. By way of example, such layout rules may determine the minimum distance between two transistors or the width of metal tracks.
After completion of the layout design, the layout is tested according to these layout rules and corrected, if appropriate. This step is called verification and is carried out by a computer. Because the components of an integrated circuit are represented by polygons in the layout, the layout rules relate to the geometrical properties of the polygons and their geometrical relationships among one another. By way of example, a diode including a p-conducting and an n-conducting region is represented by adjoining rectangles in the layout.
In the simplest case, a layout rule can relate to a single dimension. By contrast, complex layout rules relate a large number of dimensions to one another. Whereas simple layout rules can still usually be implemented by a single instruction of the verification software, the implementation of complex layout rules requires numerous instructions, the number of instructions increasing with the complexity of the layout rules. Such a process is problematic because even the processing of an individual instruction requires a high computation time or computing power because, as a rule, each instruction has to process a subset of all the polygons of a layout (for such a purpose, the polygons are stored in a database).
Furthermore, the number of instructions required for implementing a layout rule greatly depends on the “powerfulness” of the respective instruction. The instruction set of existing programming languages used to create the verification software unnecessarily restricts the possibilities for the programmer in the implementation of layout rules. Generally, at the present time, it is only possible to determine the geometrical relationships and properties, that is to say, the distances between polygons or the dimensions thereof. Furthermore, it is possible to carry out set operations, such as, for example, the formation of intersection, union, and complement sets. As a rule, the same operations can also be applied to the edges of the polygons. Under these preconditions, complex layout rules can be formulated only using numerous instructions. As a result, the computation time increases to an undesirable extent. Many layout rules are even formulated such that the instruction set of the verification software is insufficient and so-called dummy errors (purported errors) have to be accepted.